CS2000-CP

DS761PP1

13

5. APPLICATIONS

5.1

Timing Reference Clock Input

The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an

external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out-

put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock

directly affects the performance of the PLL and hence the quality of the PLL output.

5.1.1

Internal Timing Reference Clock Divider

The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on

the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal

divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls

within the valid range as indicated in Figure 7.

It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent

upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char-

acteristics” on page 8 for more details.

5.1.2

Crystal Connections (XTI and XTO)

An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-

allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 8. As shown,

nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer

to the “AC Electrical Characteristics” on page 8 for the allowed crystal frequency range.

Referenced Control

Register Location

RefClkDiv[1:0] ....................... “Reference Clock Input Divider (RefClkDiv[1:0])” on page 31

Figure 7. Internal Timing Reference Clock Divider

N

Internal Timing

Reference Clock

PLL Output

Fractional-N

Frequency

Synthesizer

Timing Reference

Clock Divider

XTI/REF_CLK

RefClkDiv[1:0]

8 MHz < SysClk < 18.75 MHz

8 MHz < RefClk <

Timing Reference Clock

50 MHz (XTI)

75 MHz (REF_CLK)

XTI

XTO

40 pF

40 pF

Figure 8. External Component Requirements for Crystal Circuit