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PCF8576DH/2 bảng dữ liệu(PDF) 23 Page - NXP Semiconductors

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PCF8576D_7
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 7 — 18 December 2008
23 of 52
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
7.16.4 Acknowledge
The number of data bytes that can be transferred from transmitter to receiver between the
START and STOP conditions is unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted
by the transmitter during which time the master generates an extra acknowledge related
clock pulse. An addressed slave receiver must generate an acknowledge after receiving
each byte. Also a master receiver must generate an acknowledge after receiving each
byte that has been clocked out of the slave transmitter. The acknowledging device must
pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold
times must be taken into consideration). A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Figure 16).
7.16.5 I2C-bus controller
The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
Fig 15. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig 16. Acknowledgement of the I2C-bus
mbc602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master



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