LPC2220 datasheet(17/50 Pages) NXP

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LPC2210_2220_6

Product data sheet

Rev. 06 — 11 December 2008

17 of 50

NXP Semiconductors

LPC2210/2220

16/32-bit ARM microcontrollers

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

VIC provides the address of the highest-priority requesting IRQs service routine,

otherwise it provides the address of a default routine that is shared by all the non-vectored

IRQs. The default routine can read another VIC register to see what IRQs are active.

6.4.1 Interrupt sources

Table 5 lists the interrupt sources for each peripheral function. Each peripheral device has

one interrupt line connected to the VIC, but may have several internal interrupt ﬂags.

Individual interrupt ﬂags may also represent more than one interrupt source.

Table 5.

Interrupt sources

Block

Flag(s)

VIC channel #

WDT

Watchdog Interrupt (WDINT)

Reserved for software interrupts only

ARM Core

EmbeddedICE, DbgCommRX

ARM Core

EmbeddedICE, DbgCommTX

TIMER0

Match 0 to 3 (MR0, MR1, MR2, MR3)

TIMER1

Match 0 to 3 (MR0, MR1, MR2, MR3)

UART0

RX Line Status (RLS)

Transmit Holding Register Empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

UART1

RX Line Status (RLS)

Transmit Holding Register empty (THRE)

RX Data Available (RDA)

Character Time-out Indicator (CTI)

Modem Status Interrupt (MSI)

PWM0

Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)

I2C

SI (state change)

SPI0

SPIF, MODF

SPI1 and SSP

SPIF, MODF and TXRIS, RXRIS, RTRIS, RORRIS

PLL

PLL Lock (PLOCK)

RTC

RTCCIF (Counter Increment), RTCALF (Alarm)

System Control

External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3)

A/D

ADC

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