PCM1789 datasheet(13/39 Pages) TI

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SYSTEM CLOCK INPUT

SystemClock

(SCKI)

High

Low

SCL

SCH

SCY

2.0V

0.8V

PCM1789

www.ti.com.............................................................................................................................................................................................. SBAS451 – OCTOBER 2008

The PCM1789 requires an external system clock input applied at the SCKI input for DAC operation. The system

clock operates at an integer multiple of the sampling frequency, or fS. The multiples supported in DAC operation

include 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS, and 1152 fS. Details for these system clock multiples are

shown in Table 1. Figure 18 and Table 2 show the SCKI timing requirements.

Table 1. System Clock Frequencies for Common Audio Sampling Rates

DEFAULT

SAMPLING

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING

FREQUENCY, fS

MODE

(kHz)

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

1152 fS

N/A

2.0480

3.0720

4.0960

6.1440

9.2160

2.0480

3.0720

4.0960

6.1440

8.1920

12.2880

18.4320

Single rate

4.0960

6.1440

8.1920

12.2880

16.3840

24.5760

36.8640

44.1

5.6448

8.4672

11.2896

16.9344

22.5792

33.8688

N/A

6.1440

9.2160

12.2880

18.4320

24.5760

36.8640

N/A

88.2

11.2896

16.9344

22.5792

33.8688

N/A

Dual rate

12.2880

18.4320

24.5760

36.8640

N/A

176.4

22.5792

33.8688

N/A

Quad rate

192

24.5760

36.8640

N/A

Figure 18. System Clock Timing Diagram

Table 2. Timing Requirements for Figure 18

SYMBOL

PARAMETER

MIN

MAX

UNIT

tSCY

System clock cycle time

tSCH

System clock width high

tSCL

System clock width low

—

System clock duty cycle

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