SPC5702BECLU datasheet(88/98 Pages) FREESCALE

88 / 98 page

MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Electrical Characteristics

Freescale Semiconductor

3.16.8

I2C Timing

Table 43. I2C Input Timing Specifications—SCL and SDA

Num

Symbol

Characteristic

Min. Value

Max. Value

Unit

1—

CC1

1 Parameter values guaranteed by design.

Start condition hold time

—

IP-Bus Cycle2

2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device

2—

CC1 Clock low time

—

IP-Bus Cycle2

4—

CC1 Data hold time

0.0

—

6—

CC1 Clock high time

—

IP-Bus Cycle2

7—

CC1 Data setup time

0.0

—

8—

CC1 Start condition setup time (for repeated start

condition only)

—

IP-Bus Cycle2

9—

CC1 Stop condition setup time

—

IP-Bus Cycle2

Table 44. I2C Output Timing Specifications—SCL and SDA

Num

Symbol

Characteristic

Min. Value

Max. Value

Unit

1 Programming IBFD (

I2C bus Frequency Divider) with the maximum frequency results in the minimum output

timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low

period. The actual position is affected by the prescale and division values programmed in IFDR.

—CC2

2 Parameter values guaranteed by design.

Start condition hold time

—

IP-Bus Cycle3

3 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device

—CC2 Clock low time

—

IP-Bus Cycle2

4 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL

or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.

—CC2 SCL/SDA rise time

—

99.6

—CC2 Data hold time

—

IP-Bus Cycle2

—CC2 SCL/SDA fall time

—

99.5

—CC2 Clock high time

—

IP-Bus Cycle2

—CC2 Data setup time

—

IP-Bus Cycle2

—CC2 Start condition setup time (for repeated start

condition only)

—

IP-Bus Cycle2

—CC2 Stop condition setup time

—

IP-Bus Cycle2

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