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CY8CTMG110
Document Number: 001-46928 Rev. *B
Page 9 of 31
Pin
No.
Type
Name
Description
Digital
Analog
20
IO
M
P2[0]
21
IO
M
P2[2]
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog column mux input.
25
IO
I, M
P0[2]
Analog column mux input.
26
IO
I, M
P0[4]
Analog column mux input.
27
IO
I, M
P0[6]
Analog column mux input.
28
Power
Vdd
Supply voltage. Bypass to ground with 0.1 uF capacitor.
29
IO
I, M
P0[7]
Analog column mux input.
30
IO
I, M
P0[5]
Analog column mux input.
31
IO
I, M
P0[3]
Analog column mux input.
32
Power
Vss
Ground. Connect to circuit ground.
EP
Power
Vss
Exposed pad is internally connected to ground. Connect to circuit ground.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Table 2. Pin Definitions - CY8CTMG110 32-Pin (QFN) (continued)
Note
3. These are the ISSP pins, that are not High Z at POR (Power On Reset). See the PSoC Mixed Signal Array Technical Reference Manual for details.
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