MPC8641D datasheet(113/140 Pages) FREESCALE

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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

113

Thermal

platform. See note regarding cfg_platform_freq in Section 17, “Signal Listings” since it is a reset

configuration pin that is related to platform frequency.

18.4.2

Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed.

For FIFO GMII mode:

FIFO TX/RX clock frequency <= platform clock frequency / 4.2

For example, if the platform frequency is 533MHz, the FIFO TX/RX clock frequency should be no more

than 127MHz

For FIFO encoded mode:

FIFO TX/RX clock frequency <= platform clock frequency / 3.2

For example, if the platform frequency is 533MHz, the FIFO TX/RX clock frequency should be no more

than 167MHz

19 Thermal

This section describes the thermal specifications of the MPC8641.

19.1

Thermal Characteristics

Table 71 provides the package thermal characteristics for the MPC8641.

Table 70. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed

MPX to

SYSCLK

Ratio

SYSCLK (MHz)

100

111

133

167

Platform/MPX Frequency (MHz) 1

SYSCLK frequency range is 66-167 MHz. Platform clock/ MPX frequency

range is 400 MHz, 500-600 MHz.

400

500

400

533

500

555

400

500

600

533

600

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