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MPC8641D bảng dữ liệu(PDF) 22 Page - Freescale Semiconductor, Inc |
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MPC8641D bảng dữ liệu(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 140 page ![]() MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1 22 Freescale Semiconductor DDR and DDR2 SDRAM 6.2 DDR SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM interface. 6.2.1 DDR SDRAM Input AC Timing Specifications Table 18 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ)=1.8 V. Table 19 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ)=2.5 V. Table 20 provides the input AC timing specifications for the DDR SDRAM interface. Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW). Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions Parameter Symbol Min Max Unit Notes AC input low voltage 400, 533 MHz 600 MHz VIL —D n_MVREF – 0.25 D n_MVREF – 0.20 V AC input high voltage 400, 533 MHz 600 MHz VIH D n_MVREF + 0.25 D n_MVREF + 0.20 — V Table 19. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions. Parameter Symbol Min Max Unit Notes AC input low voltage VIL —D n_MVREF – 0.31 V AC input high voltage VIH D n_MVREF + 0.31 — V Table 20. DDR SDRAM Input AC Timing Specifications At recommended operating conditions. Parameter Symbol Min Max Unit Notes Controller Skew for MDQS—MDQ/MECC tCISKEW ps 1, 2 600 MHz –240 240 3 533 MHz –300 300 3 400 MHz –365 365 Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be determined by the following equation: tDISKEW =+/-(T/4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. 3. Maximum DDR1 frequency is 400 MHz. |
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