MPC8640 datasheet(19/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 13 provides the DDR2 capacitance when Dn_GV

DD(typ) = 1.8 V.

Table 12. DDR2 SDRAM DC Electrical Characteristics for D

n_GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

n_GVDD

1.71

1.89

I/O reference voltage

n_MVREF 0.49 × Dn_GVDD

0.51

× Dn_GVDD

I/O termination voltage

VTT

n_MVREF –0.0

n_MVREF + 0.04

Input high voltage

VIH

n_MVREF+0.1

n_GVDD +0.3

Input low voltage

VIL

–0.3

n_MVREF – 0.125

Output leakage current

IOZ

–50

μA4

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

Notes:

1. D

n_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.

2. D

n_MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the

receiver. Peak-to-peak noise on D

n_MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to D

n_MVREF. This rail should track variations in the DC level of Dn_MVREF.

4. Output leakage is measured with all outputs disabled, 0 V

≤ VOUT ≤ Dn_GVDD.

Table 13. DDR2 SDRAM Capacitance for D

n_GVDD(typ)=1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input/output capacitance: DQ, DQS, DQS

CIO

Delta input/output capacitance: DQ, DQS, DQS

CDIO

—0.5

Note:

1. This parameter is sampled. D

n_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2, VOUT

(peak-to-peak) = 0.2 V.

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