MPC8640DEC datasheet(119/140 Pages) FREESCALE

119 / 140 page

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

119

Thermal

heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect

technology, system air temperature rise, altitude, and so on.

Due to the complexity and variety of system-level boundary conditions for today's microelectronic

equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction)

may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as

well as system-level designs.

For system thermal modeling, the MPC8640 thermal model is shown in Figure 62. Four cuboids are used

to represent this device. The die is modeled as 12.4x15.3 mm at a thickness of 0.86 mm. See Section 3,

“Power Characteristics” for power dissipation details. The substrate is modeled as a single block

33x33x1.2 mm with orthotropic conductivity: 13.5 W/(m • K) in the xy-plane and 5.3 W/(m • K) in the

z-direction. The die is centered on the substrate. The bump/underfill layer is modeled as a collapsed

thermal resistance between the die and substrate with a conductivity of 5.3 W/(m • K) in the thickness

dimension of 0.07 mm. Because the bump/underfill is modeled with zero physical dimension (collapsed

height), the die thickness was slightly enlarged to provide the correct height. The C5 solder layer is

modeled as a cuboid with dimensions 33x33x0.4 mm and orthotropic thermal conductivity of 0.034 W/(m

• K) in the xy-plane and 9.6 W/(m • K) in the z-direction. An LGA solder layer would be modeled as a

collapsed thermal resistance with thermal conductivity of 9.6W/(m • K) and an effective height of 0.1 mm.

The thermal model uses approximate dimensions to reduce grid. Please refer to the case outline for actual

dimensions.

Figure 62. Recommended Thermal Model of MPC8640

Bump and Underfill

Die

Substrate

C5 solder layer

Die

Substrate

Side View of Model (Not to Scale)

Top View of Model (Not to Scale)

Conductivity

Value

Unit

Die (12.4x15.3x0.86 mm)

Silicon

Temperature

dependent

Bump and Underfill (12.4

× 15.3 × 0.07 mm)

Collapsed Resistance

5.3

W/(m • K)

Substrate (33

× 33 × 1.2 mm)

13.5

W/(m • K)

13.5

5.3

C5 Solder layer (33

× 33 × 0.4 mm)

0.034

W/(m • K)

0.034

9.6

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