TSA1001CF datasheet(14/19 Pages) STMICROELECTRONICS

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TSA1001

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(VOL) when the data stay within the range, or in

high level state (VOH) when the data is out of the

range.

Data Ready (DR)

The Data Ready output is an image of the clock

being synchronized on the output data (D0 to D9).

This is a very helpful signal that simplifies the syn-

chronization of the measurement equipment or

the controlling DSP.

As digital output, DR goes in high impedance state

when OEB is asserted to High level as described

in the timing diagram.

DRIVING THE ANALOG INPUT

Differential inputs

The TSA1001 has been designed to obtain opti-

mum performances when being differentially driv-

en. An RF transformer is a good way to achieve

such performances.

Figure 5 describes the schematics. The input sig-

nal is fed to the primary of the transformer, while

the secondary drives both ADC inputs. The com-

mon mode voltage of the ADC (INCM) is connect-

ed to the center-tap of the secondary of the trans-

former in order to bias the input signal around this

common voltage, internally set to 0.56V. The

INCM is decoupled to maintain a low noise level

on this node. Our evaluation board is mounted

with a 1:1 ADT1-1 transformer from Minicircuits.

You might also use a higher impedance ratio (1:2

or 1:4) to reduce the driving requirement on the

analog signal source.

Each analog input can drive a 1Vpp amplitude in-

put signal, so the resultant differential amplitude is

2Vpp.

Figure 5 : Differential input configuration

Single-ended input configuration

Some applications may require a single-ended in-

put which is easily achieved with the configuration

reported on Figure 6.

In this case, it is recommended to use an

AC-coupled analog input and connect the other

analog input to the common mode voltage of the

circuit (INCM) so as to properly bias the ADC. The

INCM may remain at the same internal level

(0.56V) thus driving only a 1Vpp input amplitude,

or it must be increased to 0.9V to drive a 2Vpp

input amplitude. You will get higher performances

using a 2Vpp signal.

Figure 6 : Single-ended input configuration

Dynamic characteristics, while not being as re-

markable as for differential configuration, are still

of very good quality. Measurements done at

25Msps, 1MHz input frequency, -1dBFS input lev-

el sum up these performances. An SFDR of

-69.5dBc, an SNR of 59.5dB and an ENOB Full

Scale of 9.7bits are achieved.

REFERENCE CONNECTION

Internal reference

In the standard configuration, the ADC is biased

with the internal reference voltage. VREFM pin is

connected to Analog Ground while VREFP is

internally set to a voltage of 1.03V. It is

recommended to decouple the VREFP in order to

minimize low and high frequency noise. Refer to

Figure 7 for the schematics.

Figure 7 : Internal reference setting

TSA1001

VIN

VINB

INCM

Ω

100pF

330pF

470nF

10nF

Analog source

1:1

ADT1-1

TSA1001

VIN

VINB

INCM

Ω

100nF

330pF

470nF

10nF

Signal source

0.9V

TSA1001

VIN

VINB

VREFM

1.03V

VREFP

330pF

470nF

10nF

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