12-Bit Operation

8-Bit Operation

TSC2008

For 12-bit operation, sending the conversion result across the SPI bus takes 16 or 24 bus clocks (SCLK clock);

see Figure 31 and Figure 30. There is an additional SCLK to be added to accommodate the cycle overhead (time

between consecutive cycles) so that the total bus cycle time used for calculating the throughput is actually 17 or

25 bus clocks (SCLK clock), respectively. Using a TSC2046-compatible SDO output mode or an SDO-adjusted

output mode does not affect the transmission time.

Seven sample-and-conversions take (19 x 7) internal clocks to complete. The MAV filter loop requires 19 internal

clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6. Because the

first acquisition cycle overlaps with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles. The

total time required is (19 × 7 + 19) – 4 = 148 CCLKs plus I/O.

For 8-bit operation, sending the conversion result across the SPI bus takes 8, 16, or 24 bus clocks (SCLK clock);

see Figure 33, Figure 32, and Figure 30. There is an additional SCLK to be added to accommodate the cycle

overhead (time between consecutive cycles) so that the total bus cycle time used for calculating the throughput is

actually 9, 17, or 25 bus clocks (SCLK clock), respectively. Sending the conversion result takes 17 or 25 SCLKs

using 8-bit resolution and a TSC2046-compatible SDO output mode. If an SDO-adjusted output mode is used

with 8-bit resolution, it takes only 9 or 17 SCLKs to send the result back to host.

Seven sample-and-conversions take (16 x 7) internal clocks to complete. The MAV filter loop takes 19 internal

clocks. For VDD = 1.2V, the complete processed data cycle time calculations are shown in Table 6. Because the

first acquisition cycle is overlapped with the I/O cycle, four CCLKs must be deducted from the total CCLK cycles.

The total time required is (16 × 7 + 19) – 4 = 127 CCLKs plus I/O.

8-Bit

17 × 10

µs + 127 × 322.6ns = 211.0µs

12-Bit

25 × 10

µs + 148 × 645.2ns = 345.5µs

8-Bit

17 × 1

µs + 127 × 322.6ns = 58.0µs

12-Bit

25 × 1

µs + 148 × 645.2ns = 120.5µs

8-Bit

17 × 500ns + 127 × 322.6ns = 49.5

µs

12-Bit

25 × 500ns + 148 × 645.2ns = 108.0

µs

8-Bit

17 × 400ns + 127 × 322.6ns = 47.8

µs

12-Bit

25 × 400ns + 148 × 645.2ns = 105.5

µs

8-Bit

17 × 250ns + 127 × 322.6ns = 45.2

µs

12-Bit

25 × 250ns + 148 × 645.2ns = 101.7

µs

8-Bit

17 × 100ns + 127 × 322.6ns = 42.7

µs

12-Bit

25 × 100ns + 148 × 645.2ns = 98.0

µs

8-Bit

17 × 62.5ns + 127 × 322.6ns = 42.0

µs

12-Bit

25 × 62.5ns + 148 × 645.2ns = 97.1

µs

8-Bit

17 × 40ns + 127 × 322.6ns = 41.7

µs

12-Bit

25 × 40ns + 148 × 645.2ns = 96.5

µs

(1)

8-bit mode cycle time is calculated based on SDO-adjusted output mode.

(2)

CCLK period used for calculation is worst-case at 1.2V supply, 322.6ns.

Copyright © 2008, Texas Instruments Incorporated

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