−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

0.8

1.0

0

1024

2048

3072

4096

Code

G019

Throughput = 3 MSPS

f − Frequency − kHz

−180

−160

−140

−120

−100

−80

−60

−40

−20

0

0

300

600

900

1200

1500

G020

Throughput = 3 MSPS

PRINCIPLES OF OPERATION

REFERENCE

ADS7882

INTEGRAL NONLINEARITY

Figure 31.

FFT

Figure 32.

The ADS7882 is a member of a family of high-speed successive approximation register (SAR) analog-to-digital

converters (ADC). The architecture is based on charge redistribution, which inherently includes a sample/hold

function.

The conversion clock is generated internally. The conversion time is 200 ns max (at 5 V +VBD).

The analog input is provided to two input pins: +IN and –IN. (Note that this is pseudo differential input and there

are restrictions on –IN voltage range.) When a conversion is initiated, the difference voltage between these pins

is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from

any internal function.

The ADS7882 has a built-in 2.5-V (nominal value) reference but can operate with an external reference. When

an internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1-

µF decoupling

capacitor and a 1-

µF storage capacitor between pin 2 (REFOUT) and pins 47, 48 (REFM). The internal reference

of the converter is buffered . There is also a buffer from REFIN to CDAC. This buffer provides isolation between

the external reference and the CDAC and also recharges the CDAC during conversion. It is essential to decouple

REFOUT to AGND with a 0.1-

µF capacitor while the device operates with an external reference.

18

Submit Documentation Feedback

Copyright © 2008, Texas Instruments Incorporated

Product Folder Link(s): ADS7882