TMS320C6745PTPT2 datasheet(93/203 Pages) TI

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6.11.1 Interfacing to SDRAM

EMB_CS

EMB_CAS

EMB_RAS

EMB_WE

EMB_CLK

EMB_SDCKE

EMB_BA[1:0]

EMB_A[11:0]

EMB_WE_DQM[0]

EMB_WE_DQM[1]

EMB_D[15:0]

EMIFB

CAS

RAS

CLK

CKE

BA[1:0]

A[11:0]

LDQM

UDQM

DQ[15:0]

SDRAM

2Mx16x4

Bank

EMB_CS

EMB_CAS

EMB_RAS

EMB_WE

EMB_CLK

EMB_SDCKE

EMB_BA[1:0]

EMB_A[11:0]

EMB_WE_DQM[3:0]

EMB_D[31:0]

EMIFB

CAS

RAS

CLK

CKE

BA[1:0]

A[11:0]

DQM[3:0]

DQ[31:0]

SDRAM

2Mx32x4

Bank

TMS320C6745/6747 Floating-point Digital Signal Processor

www.ti.com

SPRS377B – SEPTEMBER 2008 – REVISED DECEMBER 2008

The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:

• Pre-charge bit is A[10]

• The number of column address bits is 8, 9, 10 or 11

• The number of row address bits is 13 (in case of mobile SDR, number of row address bits can be 9,

10, 11, 12, or 13)

• The number of internal banks is 1, 2 or 4

Figure 6-22 shows an interface between the EMIFB and a 2M

× 16 × 4 bank SDRAM device. In addition,

Figure 6-23 shows an interface between the EMIFB and a 2M

× 32 × 4 bank SDRAM device and

Figure 6-24 shows an interface between the EMIFB and two 4M

× 16 × 4 bank SDRAM devices. Refer to

Table 6-21, as an example that shows additional list of commonly-supported SDRAM devices and the

required connections for the address pins. Note that in Table 6-21, page size/column size (not indicated in

the table) is varied to get the required addressability range.

Figure 6-22. EMIFB to 2M

× 16 × 4 bank SDRAM Interface

Figure 6-23. EMIFB to 2M

× 32 × 4 bank SDRAM Interface

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Peripheral Information and Electrical Specifications

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