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TS5071N bảng dữ liệu(PDF) 20 Page - STMicroelectronics

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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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TS5071N bảng dữ liệu(HTML) 20 Page - STMicroelectronics

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Figure 6: Delayed Data Timing (short frame mode)
SERIAL CONTROL PORT TIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
fCCLK
Frequency of CCLK
2.048
MHz
tWCH
Period of CCLK High (measured from VIH to VIH)
160
ns
tWCL
Period of CCLK Low (measured from VIL to VIL)
160
ns
tRC
Rise Time of CCLK (measured from VIL to VIH)50
ns
tFC
Fall Time of CCLK (measured from VIH to VIL)50
ns
tHCS
Hold Time, CCLK Low to CS Low (CCLK1)
10
ns
tHSC
Hold Time, CCLK Low to CS High (CCLK8)
100
ns
tSSC
Setup Time, CS Transition to CCLK Low
70
ns
tSSCO
Setup Time, CS Transition to CCLK High (to insure CO is not
enabled for single byte)
50
ns
tSDC
Setup Time, CI (CI/O) Data in to CCLK low
50
ns
tHCD
Hold Time, CCLK Low to CI (CI/O) Invalid
50
ns
tDCD
Delay Time, CCLK High to CO (CI/O) Data Out Valid
(load = 100 pF plus 2 LSTTL loads)
80
ns
tDSD
Delay Time, CS Low to CO (CI/O) Valid
(applies only if separate CS used for byte 2)
80
ns
tDDZ
Delay Time, CS or CCLK9 High to CO (CI/O) High Impedance
(applies to earlier of CS high or CCLK9 high)
15
80
ns
INTERFACE LATCH TIMING
Symbol
Parameter
Min.
Typ.
Max.
Unit
tSLC
Setup Time, IL Valid to CCLK 8 of Byte 1 Low. IL as Input
100
ns
tHCL
Hold Time, IL Valid from CCLK 8 of Byte 1 Low. IL as Input
50
ns
tDCL
Delay Time, CCLK 8 of Byte 2 Low to IL.CL = 50 pF. IL as Output
200
ns
MASTER RESET PIN
Symbol
Parameter
Min.
Typ.
Max.
Unit
tWMR
Duration of Master Reset High
1
µs
TS5070 - TS5071
20/32



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