AD9522-2SLASHPCBZ datasheet(24/84 Pages) AD

24 / 84 page

AD9522-2

Rev. 0 | Page 24 of 84

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100M

10M

100k

10k

FREQUENCY (Hz)

Figure 30. Additive (Residual) Phase Noise,

CLK-to-CMOS @ 250 MHz, Divide-by-4

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100M

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100k

10k

FREQUENCY (Hz)

Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @

2212 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz

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100M

10M

100k

10k

FREQUENCY (Hz)

INTEGRATED RMS JITTER (12kHz TO 20MHz): 625fs

INTEGRATED RMS JITTER (20kHz TO 80MHz): 438fs (EXTRAPOLATED)

Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 2177 MHz;

PFD = 120 kHz; LBW = 1.92 kHz; LVDS Output = 155.52 MHz

100M

10M

100k

10k

FREQUENCY (Hz)

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INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs

Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)

@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz

62pF

33pF

240nF

C12

220nF

BYPASS

CAPACITOR

FOR LDO

820Ω

390Ω

BYPASS

Figure 34. PLL Loop Filter Used for Clock Generation Plot (See Figure 31)

1.5nF

2.2nF

4.7µF

C12

220nF

BYPASS

CAPACITOR

FOR LDO

2.1kΩ

3kΩ

BYPASS

Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 32)

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