AD9239 datasheet(22/40 Pages) AD

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AD9239

Rev. 0 | Page 22 of

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 57).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9239.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators are

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or another method), it

should be retimed by the original clock during the last step.

Refer to the AN-501 Application Note, the AN-756 Application

Note, and the Analog Dialogue article “Analog-to-Digital Converter

Clock Optimization: A Test Engineering Perspective” (Volume 42,

Number 2, February 2008) for more in-depth information about

jitter performance as it relates to ADCs (visit www.analog.com).

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0.125 ps

0.25 ps

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ANALOG INPUT FREQUENCY (MHz)

10 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 57. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation

As shown in Figure 58 to Figure 60, the power dissipated by the

AD9239 is proportional to its clock rate. The digital power

dissipation does not vary significantly because it is determined

primarily by the DRVDD supply and bias current of the digital

output drivers.

2.0

1.8

1.6

1.4

1.2

1.0

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0.1

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170

ENCODE (MSPS)

IAVDD

POWER

IDRVDD

Figure 58. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 170 MSPS

2.0

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1.6

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ENCODE (MSPS)

IAVDD

POWER

IDRVDD

Figure 59. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 210 MSPS

2.0

1.8

1.6

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ENCODE (MSPS)

IAVDD

POWER

IDRVDD

Figure 60. Supply Current vs. Encode for fIN = 84.3 MHz, fSAMPLE = 250 MSPS

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