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AD7949

Rev. A | Page 25 of 28

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7949 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. The pinout of the

AD7949, with all its analog signals on the left side and all its

digital signals on the right side, eases this task.

Avoid running digital lines under the device because these

couple noise onto the die unless a ground plane under the

AD7949 is used as a shield. Fast switching signals, such as CNV

or clocks, should not run near analog signal paths. Crossover of

digital and analog signals should be avoided.

At least one ground plane should be used. It can be common or

split between the digital and analog sections. In the latter case,

the planes should be joined underneath the AD7949s.

The AD7949 voltage reference input REF has a dynamic input

impedance and should be decoupled with minimal parasitic

inductances. This is done by placing the reference decoupling

ceramic capacitor close to, ideally right up against, the REF and

GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies VDD and VIO of the AD7949

should be decoupled with ceramic capacitors, typically 100 nF,

placed close to the AD7949 and connected using short, wide

traces to provide low impedance paths and reduce the effect of

glitches on the power supply lines.

EVALUATING AD7949 PERFORMANCE

Other recommended layouts for the AD7949 are outlined in the

documentation of the evaluation board for the AD7949 (EVAL-

AD7949CBZ). The evaluation board package includes a fully

assembled and tested evaluation board, documentation, and

software for controlling the board from a PC via the evaluation

controller board, EVAL-CONTROL BRD3.

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