DSP56725 datasheet(35/48 Pages) FREESCALE

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Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

Table 17 lists the EMC timing parameters with EMC PLL bypassed.

Table 17. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

Tclk

× Tc

—ns

Input setup to LCLK (except LGTA/LUPWAIT)

Tin_s

8—

Input hold from LCLK (except LGTA/LUPWAIT)1

Tin_h

–1

—

LGTA valid time

Tgta

—

LUPWAIT valid time

Tupwait

—

LALE negedge to LAD (address phase) invalid (address latch hold

time)

Tale_h

4—

LALE valid time

Tale

—

Output setup from LCLK (except LAD[23:0] and LALE)

Tout_s

9—

Output hold from LCLK (except LAD[23:0] and LALE)

Tout_h

8—

LAD[23:0] output setup from LCLK

Tad_s

8—

LAD[23:0] output hold from LCLK

Tad_h

7—

LCLK to output high impedance for LAD[23:0]

Tad_z

—8.1

Note: Negative hold time means the signal could be invalid before LCLK rising edge.

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