DSP56724 datasheet(33/48 Pages) FREESCALE

tên linh kiện	DSP56724

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Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

1.2.9

EMC Timing Specifications—DSP56724

Table 16 lists the EMC timing parameters with EMC PLL enabled.

NOTE

The DSP56725 device does not have an EMC module.

Table 16. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

Tclk

× Tc

—ns

LCLK skew to LSYNC_OUT

Tclk_skew

—

160

Input setup to LSYNC_IN (except LGTA/LUPWAIT)

Tin_s

3—

Input hold from LSYNC_IN (except LGTA/LUPWAIT)

Tin_h

2—

LGTA valid time

Tgta

—

LUPWAIT valid time

Tupwait

—

LALE negedge to LAD (address phase) invalid (address latch hold time)

Tale_h

3—

LALE valid time

Tale

3.8

—

Output setup from LSYNC_IN (except LAD[23:0] and LALE)

Tout_s

4—

Output hold from LSYNC_IN (except LAD[23:0] and LALE)

Tout_h

2—

LAD[23:0] output setup from LSYNC_IN

Tad_s

3.5

—

LAD[23:0] output hold from LSYNC_IN

Tad_h

1.5

—

LSYNC_IN to output high impedance for LAD[23:0]

Tad_z

—4.3

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