TDA9106 datasheet(20/30 Pages) STMICROELECTRONICS

20 / 30 page

Loop

Filter

1.6V

6.4V

1.6V

0 0.875T T

FLIP FLOP

(1.3V < V

< 6V)

4 I0

(0.80 < a < 1.30)

I2C Free Running

Adjustment

47nF

Figure 10 : Details of VCO

LOCKDET

H-LOCKCAP

COMP1

SYNC

PROCESSOR

H/HVIN

High

CHARGE

PUMP

Low

PLL

INHIBITION

VCO

PLL1INHIB

PLL1F

PHASE

ADJUST

H-POS

I2C

HPOS

Adj.

OSC

TRAMEXT

TRAMEXT SMFE *

LOCK/UNLOCK

STATUS

VSYNCIN

S/G

* SMFE : Safety Frequency Mode Enable

Figure 9 : PLL1 Block Diagram

OPERATING DESCRIPTION (continued)

An other feature is the capability for MCU to force

horizontal frequency through I

2C to 2xF0 or 3xF0

(for burn in mode or safety requirement).In this

case, inhibition switch is opened leaving PLL1 free

but voltage on PLL1 filter is forced to 2.66V for 2xF0

or 4.0V for 3xF0.

The PLL1 ensures the coincidence between the

leading edge of the synchro signal and a phase

reference obtained by comparison between the

sawtooth of the VCO and an internal DC voltage

2C adjustable between 2.8V and 4.0V (corre-

sponding to

± 10%) (see Figure 11). This voltage

has to be filtered on Pin 14 so as to optimize jitter.

The TDA9106 also includes a Lock/Unlock identi-

fication block which senses in real time wheither

PLL1 is locked on the incoming horizontal sync

signal or not. The resulting information is available

on Hlockout (see Synchro Processor). The block

function is described in Figure 12.

The NOR1 gate is receiving the phase comparator

output pulses (which also drive the charge pump).

When PLL1 is locked, on point A there is a very

small negative pulse (about 100ns) at each hori-

zontal cycle, so after RC filter, there is a high level

on Pin 13 which forces Hlockout to low level. Hys-

terisis comparator detects locking when Pin 13 is

reaching 6.5V and unlocking when Pin 13 is de-

creasing to 6.0V.

H Osc

Sawtooth

Phase REF1

H Synchro

1.6V

6.4V

2.8V<Vb<4.0V

7/8T

1/8T

Phase REF1 is obtained by comparison between the sawtooth and

a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-

sures the exact coincidence between the signals phase REF and

HSYNS. A

± T/10 phase adjustment is possible.

Figure 11 : PLL1 Timing Diagram

TDA9106

20/30

TDA9106 bảng dữ liệu(PDF) 20 Page - STMicroelectronics

TDA9106 bảng dữ liệu(HTML) 20 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

bảng dữ liệu tải về

Link URL