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TDA9105A bảng dữ liệu(PDF) 17 Page - STMicroelectronics |
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TDA9105A bảng dữ liệu(HTML) 17 Page - STMicroelectronics |
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17 / 31 page ![]() H Osc Sawtooth H Drive 1.6V 4V 6.4V 0.75T 0.25T Ts Duty Cycle Internally Shaped Flyback Flyback The duty cycle of H-drive is adjustable between 30% and 50%. Figure 16 : PLL2 Timing Diagram 20k Ω Q1 GND 0V 5 HFLY 400 Ω Figure 17 : Flyback Input Electrical Diagram OPERATING DESCRIPTION (continued) PLL2 The PLL2 ensures a constant position of the shaped flyback signal in comparison with the saw- tooth of the VCO (see Figure 13). The phase comparator of PLL2 is followed by a charge pump with a ±0.5mA (typ.) output current. The flyback input is composedof an NPN transistor. This input has to be current driven. The maximum recommanded input current is 2mA (see Figures 14 and 15). C Lockdet LOCKDET COMP1 INPUT INTERFACE CHARGE PUMP PLL INHIBITION VCO PHASE ADJUST PLL1INHIB Horizontal Adjust R0 C0 Filter High Low E2 3.2V OSC COMP2 CHARGE PUMP High Low RAP CYC EN Adjust Rapcyc Cap PHi2 PWM LOGI PWM BUFFER FLYBACK SortCOLL Flyback SortEM VB VA Horizontal Input 13 14 12 11 10 17 43 15 5 21 20 HLOCKOUT 2 4V Figure 18 : Dual PLL Block Diagram TDA9105A 17/31 |
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