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TDA7503 bảng dữ liệu(PDF) 12 Page - STMicroelectronics

tên linh kiện TDA7503
Giải thích chi tiết về linh kiện  DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS
PDF  26 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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TDA7503 bảng dữ liệu(HTML) 12 Page - STMicroelectronics

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Five Word Packet
Data Word
Frame Sync 1
Frame Sync 0
Data In
SCK
Receive
NETWORK MODE
Interrupts
Frame Sync 1
Frame Sync 0
Data In
SCK
Receive
Interrupts
NORMAL MODE
Figure 7. SSI Protocol.
The timing diagrams for the SSI Interface are
shown in Figure 7 for both Network and Normal
modes.
In Normal Mode the rising edge FSYNC starts the
internal bit counter to allow data to be clocked in
or out. When bit count is equal to the pro-
grammed word length the counter is reset and
the shift register is broadside loaded into the data
register. Additional SCK pulses are ignored after
the counter is reset. The next word is clocked in
or out starting with the next rising edge of
FSYNC.
In Network Mode the rising edge FSYNC starts
the internal bit counter to allow data to be clocked
in or out. When bit count is equal to the pro-
grammed word length the counter is reset and
the shift register is broadside loaded into the data
register. At this point the FSRSD bit is set indicat-
ing that a frame sync was received with that
word. After being reset the counter continues
counting, clocking in the next word. Only when
the next rising edge of FSYNC is detected is the
packet considered complete.
TDA7503
12/26



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