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M38K09RFS bảng dữ liệu(PDF) 289 Page - Renesas Technology Corp |
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M38K09RFS bảng dữ liệu(HTML) 289 Page - Renesas Technology Corp |
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289 / 328 page ![]() 3.4 List of registers Rev.2.00 Oct 05, 2006 page 48 of 89 38K0 Group REJ09B0337-0200 APPENDIX Fig. 3.4.25 Structure of EP02 control register 3 Fig. 3.4.26 Structure of EP03 control register 3 b7 b0 B1VAL02 b7:b1 – – 0 – EP02 control register 3 (EP02CON3) [address 001C16] Bit name Bit symbol At reset Function H/W S/W O O O O –: State remaining Buffer 1 enable bit Not used When the selected endpoint is IN, writing “1” to this bit makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing “1” to this bit makes data reception possible (SIE is possible to write). In double buffer mode this bit is valid. Write “0” when writing. “0” is read when reading. 00 0 00 0 0 W R b7 b0 B1VAL03 b7:b1 – – 0 – EP03 control register 3 (EP03CON3) [address 001C16] Bit name Bit symbol At reset Function H/W S/W O O O O –: State remaining Buffer 1 enable bit Not used When the selected endpoint is IN, writing “1” to this bit makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing “1” to this bit makes data reception possible (SIE is possible to write). In double buffer mode this bit is valid. Write “0” when writing. “0” is read when reading. 0000 000 W R Fig. 3.4.24 Structure of EP01 control register 3 b7 b0 B1VAL01 b7:b1 – – 0 – EP01 control register 3 (EP01CON3) [address 001C16] Bit name Bit symbol At reset Function H/W S/W O O O O –: State remaining Buffer 1 enable bit Not used When the selected endpoint is IN, writing “1” to this bit makes the transmitting data a set state (SIE is possible to read). When the selected endpoint is OUT, writing “1” to this bit makes data reception possible (SIE is possible to write). In double buffer mode this bit is valid. Write “0” when writing. “0” is read when reading. 0000 000 W R |
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