M38K09RFS datasheet(265/328 Pages) RENESAS

265 / 328 page

3.2 Notes on use

Rev.2.00

Oct 05, 2006

page 24 of 89

38K0 Group

REJ09B0337-0200

APPENDIX

3.2.5 Notes on serial I/O

(1)

Notes when selecting clock synchronous serial I/O (Serial I/O)

➀ Stop of transmission operation

Clear the serial I/O enable bit and the transmit enable bit to “0” (Serial I/O and transmit disabled).

q Reason

Since transmission is not stopped and the transmission circuit is not initialized even if only the

serial I/O enable bit is cleared to “0” (Serial I/O disabled), the internal transmission is running (in

this case, since pins TxD, RxD, SCLK, and SRDY function as I/O ports, the transmission data is not

output). When data is written to the transmit buffer register in this state, data starts to be shifted

to the transmit shift register. When the serial I/O enable bit is set to “1” at this time, the data during

internally shifting is output to the TxD pin and an operation failure occurs.

➁ Stop of receive operation

Clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (Serial

I/O disabled).

➂ Stop of transmit/receive operation

Clear the transmit enable bit and receive enable bit to “0” simultaneously (transmit and receive

disabled).

(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data

transmission and reception cannot be stopped.)

q Reason

In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.

If any one of transmission and reception is disabled, a bit error occurs because transmission and

reception cannot be synchronized.

In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,

the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit

disabled). Also, the transmission circuit is not initialized by clearing the serial I/O enable bit to “0”

(Serial I/O disabled) (refer to (1) ➀).

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