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4513 bảng dữ liệu(PDF) 149 Page - Renesas Technology Corp |
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4513 bảng dữ liệu(HTML) 149 Page - Renesas Technology Corp |
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149 / 210 page ![]() APPLICATION 2.4 Serial I/O 2-46 4513/4514 Group User’s Manual Fig. 2.4.5 Master serial I/O setting example g0 h b3 b0 Disable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE Interrupt control register V2 “0” ! ! All interrupts disabled (DI instruction) Serial I/O interrupt occurrence disabled (TV2A instruction) 0 ! Set Serial I/O Serial I/O mode register J1 b3 b0 1 1 ! Internal clock selected (TJ1A instruction) Serial I/O port selected Dividing ratio = 4 selected 1 g0 h Clear Interrupt Request Serial I/O interrupt activated condition is cleared. Serial I/O transmit/receive completion flag SIOF “0” Serial I/O interrupt activated condition cleared (SNZSI instruction) Note when the interrupt request is cleared When is executed, considering the skip of the next instruction according to the SIOF flag, insert the NOP instruction after the SNZSI instruction. When interrupt is not used When interrupt is used Set Interrupt Interrupts except serial I/O is enabled (EI instruction) Set Interrupt Serial I/O interrupt temporarily disabled is enabled. b3 b0 1 !!! Interrupt control register V2 Serial I/O interrupt occurrence enabled (TV2A instruction) Interrupt enable flag INTE “1” All interrupts enabled (EI instruction) Start Condition of Serial I/O operation Slave side is enabled to receive is checked. Pin level of control signal = “L” Start Serial I/O Operation Serial transfer is started (SST instruction) after checking slave side is enabled to receive. Check Serial I/O Interrupt Request SIOF flag is checked (SNZSI instruction). Serial I/O Interrupt Occur Execute Receive Data Data received by serial transfer is executed. Register SI → register A, register B (TABSI instruction) “!”: it can be “0” or “1.” When serial communication is executed, to are repeated. |
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