7751 datasheet(39/540 Pages) RENESAS

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7751 Group User’s Manual

CENTRAL PROCESSING UNIT (CPU)

2–20

2.4 Memory assignment

Timer A0

Timer A4

Timer A3

Timer A2

Timer A1

Timer B2

Timer B1

Timer B0

A-D conversion

UART1 transmit

UART1 receive

UART0 transmit

UART0 receive

INT2

INT1

INT0

Watchdog timer

DBC (Note 1)

BRK instruction

zero divide

RESET

FFD616

FFD816

FFDA16

FFDC16

FFDE16

FFE016

FFE216

FFE816

FFEC16

FFE416

FFE616

FFEA16

FFEE16

FFF016

FFF216

FFF416

FFF616

FFF816

FFFA16

FFFC16

FFFE16

Interrupt vector table

00007F16

00000016

00008016

00FFFF16

00FFD616

Internal RAM area

Refer to Figure 2.4.2.

Notes 1: DBC is an interrupt only for debugging; do not use this interrupt.

2: Access to the internal ROM area is disabled in the microprocessor mode.

(Refer to section “2.5 Processor modes.” )

3: Memory assignment of internal area varies according to the type of microcomputer.

Refer to “Appendix 1. Memory assignment” for other products.

Internal ROM area

SFR area

00400016

00087F16

M37751M6C-XXXFP

: The internal memory is not assigned.

Fig. 2.4.1 Internal area’s memory assignment

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