SH7763 datasheet(13/2026 Pages) RENESAS

13 / 2026 page

Rev. 1.00 Oct. 01, 2007 Page xiii of lxvi

9.3.4

Interrupt Source Register (INTREQ) .................................................................... 250

9.3.5

Interrupt Mask Register 0 (INTMSK0) ................................................................ 251

9.3.6

Interrupt mask register 1 (INTMSK1) .................................................................. 253

9.3.7

Interrupt mask register 2 (INTMSK2) .................................................................. 254

9.3.8

Interrupt Mask Clear Register 0 (INTMSKCLR0) ............................................... 257

9.3.9

Interrupt mask clear register 1 (INTMSKCLR1).................................................. 259

9.3.10 Interrupt mask clear register 2 (INTMSKCLR2).................................................. 260

9.3.11 NMI Flag Control Register (NMIFCR) ................................................................ 263

9.3.12 User Interrupt Mask Level Register (USERIMASK) ........................................... 264

9.3.13 On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13) ............ 266

9.3.14 Interrupt Source Register 0 (Mask State is not affected) (INT2A0) ..................... 268

9.3.15 Interrupt Source Register 01 (Mask State is not affected) (INT2A01) ................. 269

9.3.16 Interrupt Source Register (Mask State is affected) (INT2A1) .............................. 272

9.3.17 Interrupt Source Register 11 (Mask State is affected) (INT2A11) ....................... 274

9.3.18 Interrupt Mask Register (INT2MSKR)................................................................. 276

9.3.19 Interrupt Mask Register 1 (INT2MSKR1)............................................................ 277

9.3.20 Interrupt Mask Clear Register (INT2MSKCR)..................................................... 279

9.3.21 Interrupt Mask Clear Register 1 (INT2MSKCR1)................................................ 281

9.3.22 On-chip Module Interrupt Source Registers (INT2B0 to INT2B7 and

INT2B9 to INT2B11) ........................................................................................... 283

9.3.23 GPIO Interrupt Set Register (INT2GPIC) .............................................................. 289

9.4

Interrupt Sources................................................................................................................ 292

9.4.1

NMI Interrupt........................................................................................................ 292

9.4.2

IRQ Interrupts ....................................................................................................... 292

9.4.3

IRL Interrupts ....................................................................................................... 293

9.4.4

On-chip Module Interrupts ................................................................................... 295

9.4.5

Interrupt Priority Level of On-chip Module Interrupts ......................................... 295

9.4.6

Interrupt Exception Handling and Priority............................................................ 296

9.5

Operation ........................................................................................................................... 305

9.5.1

Interrupt Sequence ................................................................................................ 305

9.5.2

Multiple Interrupts ................................................................................................ 307

9.5.3

Interrupt Masking by MAI Bit .............................................................................. 307

9.6

Interrupt Response Time.................................................................................................... 308

9.7

Usage Notes ....................................................................................................................... 309

9.7.1

Example of Interrupt Handling Routine for Level-Encoded IRL and

Level-Sensed IRQ................................................................................................. 309

9.7.2

Notes on Setting IRQ7/

IRL7 to IRQ0/IRL0 Pin Function.................................... 310

9.7.3

To Clear IRQ and IRL Interrupt Requests ............................................................ 310

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