32171 datasheet(49/772 Pages) RENESAS

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2-5

32171 Group User's Manual (Rev.2.00)

BPC

31(LSB)

0(MSB)

CPU

2.3 Control Registers

2.3.2 Condition Bit Register: CBR (CR1)

The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the

Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register

is a read-only register (writes to this register by "MVTC" instruction are ignored).

2.3.3 Interrupt Stack Pointer: SPI (CR2)

User Stack Pointer: SPU (CR3)

The Interrupt Stack Pointer (SPI) and User Stack Pointer (SPU) hold the current address of the

stack pointer. These registers can be accessed as general-purpose register R15. In this case,

whether R15 is used as SPI or as SPU depends on the PSW's Stack Mode (SM) bit.

2.3.4 Backup PC: BPC (CR6)

The Backup PC (BPC) is a register used to save the value of the Program Counter (PC) when an

EIT occurs. Bit 31 is fixed to 0.

When an EIT occurs, the value held in the PC immediately before the EIT occurred or the value of

the next instruction is set in this register. When the "RTE" instruction is executed, the saved value

is returned from the BPC to the PC. However, the two low-order bits of the PC when thus returned

are always fixed to "00" (control always returns to word boundaries.)

SPI

SPU

0(MSB)

31(LSB)

CBR

0(MSB)

31(LSB)

00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 00 00 0 0 0 C

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