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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SH7047 bảng dữ liệu(PDF) 86 Page - Renesas Technology Corp |
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SH7047 bảng dữ liệu(HTML) 86 Page - Renesas Technology Corp |
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86 / 764 page  Rev. 2.00, 09/04, page 46 of 720 The clock mode is selected by the input of MD2 and MD3 pins. Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode Pin Setting MD3 MD2 Maximum Operating Clock Frequency 0 0 12.5 MHz (Input clock × 1*, maximum of input clock: 12.5 MHz) 0 1 25 MHz (Input clock × 2*, maximum of input clock: 12.5 MHz) 1 0 40 MHz (Input clock × 4*, maximum of input clock: 10 MHz) 1 1 50 MHz (Input clock × 4 for system clock, Input clock × 2 for peripheral clock, maximum of input clock: 12.5 MHz) Note: * The frequencies for the system and peripheral module clocks are the same. 3.2 Input/Output Pins Table 3.3 describes the configuration of operating mode related pins. Table 3.3 Operating Mode Pin Configuration Pin Name Input/Output Function MD0 Input Designates operating mode through the level applied to this pin MD1 Input Designates operating mode through the level applied to this pin MD2 Input Designates clock mode through the level applied to this pin MD3 Input Designates clock mode through the level applied to this pin FWP Input Pin for the hardware protection against programming/erasing the on-chip flash memory |
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