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32176 bảng dữ liệu(HTML) 93 Page - Renesas Technology Corp |
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93 / 742 page  4 EIT 4-5 32176 Group Hardware Manual Rev.1.10 REJ09B0067-0110 Jun 20.06 When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the content of the PC and PSW registers is transferred to the backup register (BPC register and BPSW field in the PSW register). Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC register and PSW register (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator must be saved to the stack as necessary. Remember that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the content of the backup register (BPC register and BPSW field in the PSW register) is returned to the PC and PSW registers. Note that the values stored in the BPC and the PSW register’s BPSW field after executing the RTE instruction are undefined. 4.3 EIT Processing Procedure |
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