SH7785 datasheet(73/1692 Pages) RENESAS

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2. Programming Model

Rev.1.00 Jan. 10, 2008 Page 43 of 1658

REJ09B0261-0100

2.7

Usage Notes

2.7.1

Notes on Self-Modifying Code

To accelerate the processing speed, the instruction prefetching capability of this LSI has been

significantly enhanced from that of the SH-4. Therefore, in the case when a code in memory is

rewritten and attempted to be executed immediately, there is increased possibility that the code

before being modified, which has already been prefetched, is executed.

To ensure execution of the modified code, one of the following sequence of instructions should be

executed between the code rewriting instruction and execution of the modified code.

(1)

When the Codes to be Modified are in Non-Cacheable Area

SYNCO

ICBI @Rn

The target for the ICBI instruction can be any address within the range where no address error

exception occurs.

(2)

When the Codes to be Modified are in Cacheable Area (Write-Through)

SYNCO

ICBI @Rn

All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI

instruction. The ICBI instruction should be issued to each cache line. One cache line is 32 bytes.

(3)

When the Codes to be Modified are in Cacheable Area (Copy-Back)

OCBP @Rm or OCBWB @Rm

SYNCO

ICBI @Rn

All operand cache areas corresponding to the modified codes should be written back to the main

memory by the OCBP or OCBWB instruction. Then all instruction cache areas corresponding to

the modified codes should be invalidated by the ICBI instruction. The OCBP, OCBWB, and ICBI

instruction should be issued to each cache line. One cache line is 32 bytes.

Note:

Self-modifying code is the processing which executes instructions while dynamically

rewriting the codes in memory.

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