7643_06 datasheet(13/424 Pages) RENESAS

13 / 424 page

Rev.2.00

Aug 28, 2006

page 9 of 12

7643 Group

REJ09B0133-0200

Fig. 2.6.48 Control procedure (2) ............................................................................................... 153

Fig. 2.6.49 Connection diagram .................................................................................................. 154

Fig. 2.6.50 Register setting (1) ................................................................................................... 155

Fig. 2.6.51 Register setting (2) ................................................................................................... 156

Fig. 2.6.52 Register setting (3) ................................................................................................... 157

Fig. 2.6.53 Register setting (4) ................................................................................................... 158

Fig. 2.6.54 Control procedure (1) ............................................................................................... 159

Fig. 2.6.55 Control procedure (2) ............................................................................................... 160

Fig. 2.6.56 Electronic instrument application example ............................................................. 161

Fig. 2.6.57 Encryption sytem application example ................................................................... 162

Fig. 2.6.58 Peripheral circuit example ........................................................................................ 164

Fig. 2.6.59 LPF peripheral circuit ............................................................................................... 164

Fig. 2.6.60 Connection of insulation connector ........................................................................ 164

Fig. 2.7.1 Memory map of registers related to frequency synthesizer .................................. 167

Fig. 2.7.2 Structure of CPU mode register A ........................................................................... 168

Fig. 2.7.3 Structure of Frequency synthesizer control register .............................................. 168

Fig. 2.7.4 Structure of Frequency synthesizer multiply register 1 ......................................... 169

Fig. 2.7.5 Structure of Frequency synthesizer multiply register 2 ......................................... 169

Fig. 2.7.6 Structure of Frequency synthesizer divide register ................................................ 170

Fig. 2.7.7 Block diagram for frequency synthesizer circuit ..................................................... 171

Fig. 2.7.8 Frequency synthesizer multiply register 2 setting example .................................. 171

Fig. 2.7.9 Frequency synthesizer multiply register 1 setting example .................................. 172

Fig. 2.7.10 Frequency synthesizer divide register setting example ....................................... 172

Fig. 2.8.1 Memory map of registers related to external devices connection ....................... 174

Fig. 2.8.2 Structure of CPU mode register A ........................................................................... 175

Fig. 2.8.3 Structure of CPU mode register B ........................................................................... 175

Fig. 2.8.4 Software wait timing example .................................................................................... 177

Fig. 2.8.5 RDY wait timing example ........................................................................................... 178

Fig. 2.8.6 Extended RDY wait (software wait plus RDY input anytime wait) timing example ...... 179

Fig. 2.8.7 Hold function timing diagram ..................................................................................... 180

Fig. 2.8.8 Connection example of memory access up to 256 Kbytes .................................. 181

Fig. 2.8.9 External ROM and RAM example ............................................................................. 182

Fig. 2.8.10 RDY function use example ...................................................................................... 183

Fig. 2.8.11 Read cycle (OE access, SRAM) ............................................................................. 184

Fig. 2.8.12 Read cycle (OE access, EPROM) .......................................................................... 184

Fig. 2.8.13 Write cycle (W control, SRAM) ............................................................................... 185

Fig. 2.9.1 RAM backup system ................................................................................................... 188

Fig. 2.10.1 Memory map of registers related to clock generating circuit ............................. 189

Fig. 2.10.2 Structure of CPU mode register A ......................................................................... 190

Fig. 2.10.3 Structure of Clock control register .......................................................................... 190

Fig. 2.10.4 Structure of Frequency synthesizer control register ............................................ 191

Fig. 2.10.5 Structure of Frequency synthesizer multiply register 1 ....................................... 191

Fig. 2.10.6 Structure of Frequency synthesizer multiply register 2 ....................................... 192

Fig. 2.10.7 Structure of Frequency synthesizer divide register .............................................. 192

Fig. 2.10.8 Connection diagram .................................................................................................. 195

Fig. 2.10.9 Status transition diagram during power failure ..................................................... 195

Fig. 2.10.10 Setting of relevant registers .................................................................................. 196

Fig. 2.10.11 Control procedure ................................................................................................... 197

Fig. 2.10.12 Structure of clock counter ...................................................................................... 198

Fig. 2.10.13 Initial setting of relevant registers ........................................................................ 199

Fig. 2.10.14 Setting of relevant registers after detecting power failure ................................ 200

Fig. 2.10.15 Control procedure (1) ............................................................................................. 201

Fig. 2.10.16 Control procedure (2) ............................................................................................. 202

List of figures

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