7641 datasheet(11/385 Pages) RENESAS

11 / 385 page

Rev.2.00

Aug 28, 2006

page 7 of 13

7641 Group

REJ09B0336-0200

Fig. 2.3.1 Memory map of registers related to serial I/O ......................................................... 38

Fig. 2.3.2 Structure of Serial I/O shift register ........................................................................... 39

Fig. 2.3.3 Structure of Serial I/O control register 1 ................................................................... 39

Fig. 2.3.4 Structure of Serial I/O control register 2 ................................................................... 40

Fig. 2.3.5 Structure of Interrupt request register C ................................................................... 41

Fig. 2.3.6 Structure of Interrupt control register C ..................................................................... 41

Fig. 2.3.7 Serial I/O connection examples (1) ............................................................................ 42

Fig. 2.3.8 Serial I/O connection examples (2) ............................................................................ 43

Fig. 2.3.9 Connection diagram ...................................................................................................... 44

Fig. 2.3.10 Timing chart ................................................................................................................. 44

Fig. 2.3.11 Registers setting for transmitter ................................................................................ 45

Fig. 2.3.12 Setting of serial I/O transmission data .................................................................... 45

Fig. 2.3.13 Control procedure of transmitter ............................................................................... 46

Fig. 2.3.14 Connection diagram .................................................................................................... 47

Fig. 2.3.15 Registers setting for SPI compatible mode ............................................................. 48

Fig. 2.3.16 Control procedure of SPI compatible mode in slave ............................................. 49

Fig. 2.3.17 Control procedure of SPI compatible mode in master .......................................... 50

Fig. 2.4.1 Memory map of registers related to UART ............................................................... 52

Fig. 2.4.2 Structure of UARTx (x = 1, 2) mode register ........................................................... 53

Fig. 2.4.3 Structure of UARTx (x = 1, 2) control register ......................................................... 54

Fig. 2.4.4 Structure of UARTx (x = 1, 2) status register .......................................................... 55

Fig. 2.4.5 Structure of UARTx (x = 1, 2) RTS control register ................................................ 55

Fig. 2.4.6 Structure of UARTx (x = 1, 2) baud rate generator ................................................ 56

Fig. 2.4.7 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2 ................... 57

Fig. 2.4.8 Structure of Interrupt request register A .................................................................... 58

Fig. 2.4.9 Structure of Interrupt request register B .................................................................... 58

Fig. 2.4.10 Structure of Interrupt control register A ................................................................... 59

Fig. 2.4.11 Structure of Interrupt control register B ................................................................... 59

Fig. 2.4.12 UART transfer data format ........................................................................................ 60

Fig. 2.4.13 Connection diagram .................................................................................................... 66

Fig. 2.4.14 Timing chart ................................................................................................................. 66

Fig. 2.4.15 Registers setting for transmitter ................................................................................ 67

Fig. 2.4.16 Registers setting for receiver (1) .............................................................................. 68

Fig. 2.4.17 Registers setting for receiver (2) .............................................................................. 69

Fig. 2.4.18 Control procedure of transmitter ............................................................................... 70

Fig. 2.4.19 Control procedure of receiver .................................................................................... 71

Fig. 2.4.20 Connection diagram .................................................................................................... 73

Fig. 2.4.21 Registers setting related to UART address mode .................................................. 74

Fig. 2.4.22 Control procedure (1) ................................................................................................. 75

Fig. 2.4.22 Control procedure (2) ................................................................................................. 76

Fig. 2.5.1 Memory map of registers related to DMAC .............................................................. 79

Fig. 2.5.2 Structure of DMAC index and status register ........................................................... 80

Fig. 2.5.3 Structure of DMAC channel x (x = 0, 1) mode register 1 ...................................... 81

Fig. 2.5.4 Structure of DMAC channel 0 mode register 2 ........................................................ 83

Fig. 2.5.5 Structure of DMAC channel 1 mode register 2 ........................................................ 84

Fig. 2.5.6 Structure of DMAC channel x source registers Low, High ..................................... 85

Fig. 2.5.7 Structure of DMAC channel x destination registers Low, High .............................. 85

Fig. 2.5.8 Structure of DMAC channel x transfer count registers Low, High ......................... 86

Fig. 2.5.9 Structure of Interrupt request register A .................................................................... 87

Fig. 2.5.10 Structure of Interrupt control register A ................................................................... 87

Fig. 2.5.11 Transfer mode overview ............................................................................................. 88

Fig. 2.5.12 Basic operation of registers transferring .................................................................. 89

List of figures

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