H83397 datasheet(86/747 Pages) RENESAS

tên linh kiện	H83397

Giải thích chi tiết về linh kiện	Single-Chip Microcomputer

PDF	747 Pages

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Reset state

Hardware

standby mode

Interrupt request

RES = 1

Power-down state

Sleep mode

Exception-

handling state

Program

execution state

Exception

handling

request

End of exception

handing

SLEEP instruction

with SSBY bit set

STBY = 1, RES = 0

SLEEP

instruction

Software

standby mode

NMI, IRQ0

to IRQ2 or IRQ6

Notes: 1.

A transition to the reset state occurs when

RES goes low, except when the chip

is in the hardware standby mode.

A transition from any state to the hardware standby mode occurs when

STBY

goes low.

Figure 2.12 State Transitions

2.6.2

Program Execution State

In this state the CPU executes program instructions.

2.6.3

Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU is reset or interrupted

and changes its normal processing flow. In interrupt exception handling, the CPU references the

stack pointer (R7) and saves the program counter and condition code register on the stack. For

further details see section 4, Exception Handling.

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