H8SXSLASH1663M datasheet(295/1504 Pages) RENESAS

tên linh kiện	H8SX/1663M

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 263 of 1468

REJ09B0412-0200

9.7.6

Read Strobe (

RD)

When the byte control SRAM space is specified, the RDNCR setting for the corresponding space

is invalid.

The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface.

Note that the

RD timing with respect to the DACK and EDACK rising edge becomes different.

9.7.7

Extension of Chip Select (

CS) Assertion Period

In the byte control SRAM interface, the extension cycles can be inserted before and after the bus

cycle in the same way as the basic bus interface. For details, refer to section 9.6.6, Extension of

Chip Select (

CS) Assertion Period.

9.7.8

DACK and EDACK Signal Output Timing

For DMAC or EXDMAC single address transfers, the

DACK and EDACK signal assert timing

can be modified by using the DKC and EDKC bits in BCR1.

Figure 9.28 shows the

DACK and EDACK signal output timing. Setting the DKC bit or the

EDKC bit to 1 asserts the

DACK or EDACK signal a half cycle earlier.

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