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H8SX/1663M bảng dữ liệu(PDF) 1150 Page - Renesas Technology Corp

tên linh kiện H8SX/1663M
Giải thích chi tiết về linh kiện  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Section 25 Flash Memory
Rev. 2.00 Sep. 24, 2008 Page 1118 of 1468
REJ09B0412-0200
Table 25.3
Registers/Parameters and Target Modes
Register/Parameter
Down-
load
Initiali-
zation
Program-
ming
Erasure
Read
RAM
Emulation
FCCS
O
FPCS
O
FECS
O
FKEY
O
O
O
FMATS
O*
1
O*
1
O*
2
Programming/
erasing interface
registers
FTDAR
O
DPFR
O
FPFR
O
O
O
FPEFEQ
O
FMPAR
O
FMPDR
O
Programming/
erasing interface
parameters
FEBS
O
RAM emulation
RAMER
O
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target memory MAT.
25.7.1
Programming/Erasing Interface Registers
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a reset.
(1)
Flash Code Control/Status Register (FCCS)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
7
1
R
6
0
R
5
0
R
4
FLER
0
R
3
0
R
0
SCO
0
(R)/W*
2
0
R
1
0
R
Bit
Bit Name
Initial Value
R/W
Note:
*
This is a write-only bit. This bit is always read as 0.



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