H8SXSLASH1663M datasheet(523/1504 Pages) RENESAS

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Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 491 of 1468

REJ09B0412-0200

11.5.4

Bus Mode

There are two bus modes: cycle steal mode and burst mode.

For auto-request activation, either cycle steal mode or burst mode can be selected by the DTF0 bit

in EDMDR. When the activation source is an external request, cycle steal mode is used.

(1)

Cycle Steal Mode

In cycle steal mode, the EXDMAC releases the bus mastership at the end of each transfer of a

transfer unit (byte, word, longword, one block size, or one cluster size). If there is a subsequent

transfer request, the EXDMAC takes back the bus mastership, performs another transfer-unit

transfer, and then releases the bus mastership again at the end of the transfer. This procedure is

repeated until the transfer end condition is satisfied.

If a transfer request occurs in another channel during EXDMA transfer, the bus mastership is

temporarily released for another bus master, then transfer is performed on the channel for which

the transfer request was issued. For details on the operation when there are transfer requests for a

number of channels, see section 11.5.8, Channel Priority Order.

Figure 11.13 shows an example of the timing in cycle steal mode. The transfer conditions are as

follows:

• Address mode: Single address mode

• Sampling method on the EDREQ pin: Low level sensing

• CPU internal bus master is operating in external space

CPU

EXDMAC

CPU

EXDMAC

EDREQ

EDRAK

Bus cycle

Bus mastership returned temporarily to CPU

Figure 11.13 Example of Timing in Cycle Steal Mode

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