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H8SX/1663M bảng dữ liệu(PDF) 491 Page - Renesas Technology Corp |
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H8SX/1663M bảng dữ liệu(HTML) 491 Page - Renesas Technology Corp |
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491 / 1504 page ![]() Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 459 of 1468 REJ09B0412-0200 11.3.1 EXDMA Source Address Register (EDSAR) EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when the address specified by EDDAR is transferred as a destination address (DIRS = 1 in EDACR). EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress. 31 0 R/W 30 0 R/W 29 0 R/W 28 0 R/W 27 0 R/W 24 0 R/W 26 0 R/W 25 0 R/W Bit Bit Name Initial Value R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 16 0 R/W 18 0 R/W 17 0 R/W Bit Bit Name Initial Value R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 8 0 R/W 10 0 R/W 9 0 R/W Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 0 0 R/W 2 0 R/W 1 0 R/W Bit Bit Name Initial Value R/W |
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