H8SXSLASH1663M datasheet(386/1504 Pages) RENESAS

tên linh kiện	H8SX/1663M

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 354 of 1468

REJ09B0412-0200

(6)

Relationship between Chip Select (

CS) Signal and Read (RD) Signal

Depending on the system's load conditions, the

RD signal may lag behind the CS signal. An

example is shown in figure 9.98. In this case, with the setting for no idle cycle insertion (a), there

may be a period of overlap between the

RD signal in bus cycle A and the CS signal in bus cycle B.

Setting idle cycle insertion, as in (b), however, will prevent any overlap between the

RD and CS

signals. In the initial state after reset release, idle cycle indicated in (b) is set.

Bus cycle A

Bus cycle B

Address bus

CS (area A)

CS (area B)

Bus cycle A

Bus cycle B

Overlap time may occur between the

CS (area B) and RD

(a) No idle cycle inserted

(IDLS1 = 0)

(b) Idle cycle inserted

(IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)

Figure 9.98 Relationship between Chip Select (

CS) and Read (RD)

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