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H8SX/1663R bảng dữ liệu(PDF) 264 Page - Renesas Technology Corp

tên linh kiện H8SX/1663R
Giải thích chi tiết về linh kiện  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 232 of 1468
REJ09B0412-0200
Interface
Description
Area Name
DRAM interface
Directly connected to DRAM
DRAM space
Synchronous DRAM interface
Directly connected to
synchronous DRAM
Synchronous DRAM space
Table 9.5
Areas Specifiable for Each Interface
Areas
Interface
Related
Registers
0
1
2
3
4
5
6
7
Basic interface
O
O
O
O
O
O
O
O
Byte control SRAM interface
SRAMCR
O
O
O
O
O
O
O
O
Burst ROM interface
BROMCR
O
O
Address/data multiplexed I/O
interface
MPXCR
O
O
O
O
O
DRAM interface
O
Synchronous DRAM interface
DRAMCR
O
(2)
Bus Width
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is
selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions
as a 16-bit access space. In addition, the bus width of address/data multiplexed I/O space is 8 bits
or 16 bits, and the bus width for the byte control SRAM space is 16 bits.
The initial state of the bus width is specified by the operating mode.
If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as
16-bit access space, 16-bit bus mode is set.
(3)
Endian Format
Though the endian format of this LSI is big endian, data can be converted into little endian format
when reading or writing to the external address space.
Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in
ENDIANCR.
The initial state of each area is the big endian format.
Note that the data format for the areas used as a program area or a stack area should be big endian.



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