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H8SX/1663R bảng dữ liệu(PDF) 154 Page - Renesas Technology Corp

tên linh kiện H8SX/1663R
Giải thích chi tiết về linh kiện  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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Section 6 Exception Handling
Rev. 2.00 Sep. 24, 2008 Page 122 of 1468
REJ09B0412-0200
When an address error occurs, the following is performed to halt the DTC, DMAC, and
EXDMAC.
• The ERR bit of DTCCR in the DTC is set to 1.
• The ERRF bit of DMDR_0 in the DMAC is set to 1.
• The ERRF bit of EDMDR_0 in the EXDMAC is set to 1.
• The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate
transfer.
• The DTE bits of EDMDRs for all channels in the EXDMAC are cleared to 0 to forcibly
terminate transfer.
Table 6.6 shows the state of CCR and EXR after execution of the address error exception
handling.
Table 6.6
Status of CCR and EXR after Address Error Exception Handling
CCR
EXR
Interrupt Control Mode
I
UI
T
I2 to I0
0
1
2
1
0
7
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.



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