H8SXSLASH1663R datasheet(152/1504 Pages) RENESAS

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Section 6 Exception Handling

Rev. 2.00 Sep. 24, 2008 Page 120 of 1468

REJ09B0412-0200

6.5

Address Error

6.5.1

Address Error Source

Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address

error.

Table 6.5

Bus Cycle and Address Error

Bus Cycle

Type

Bus Master

Description

Address Error

Fetches instructions from even addresses

No (normal)

Fetches instructions from odd addresses

Occurs

Fetches instructions from areas other than on-chip

peripheral module space*

No (normal)

Fetches instructions from on-chip peripheral

module space*

Occurs

Fetches instructions from external memory space

in single-chip mode

Occurs

Instruction

fetch

CPU

Fetches instructions from access prohibited

area.*

Occurs

Accesses stack when the stack pointer value is

even address

No (normal)

Stack

operation

CPU

Accesses stack when the stack pointer value is

odd address

Occurs

Accesses word data from even addresses

No (normal)

Accesses word data from odd addresses

No (normal)

Accesses external memory space in single-chip

mode

Occurs

Data read/write CPU

Accesses to access prohibited area*

Occurs

Accesses word data from even addresses

No (normal)

Accesses word data from odd addresses

No (normal)

Accesses external memory space in single-chip

mode

Occurs

Data read/write DTC or

DMAC

Accesses to access prohibited area*

Occurs

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