H8SXSLASH1663R datasheet(367/1504 Pages) RENESAS

367 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 335 of 1468

REJ09B0412-0200

(3)

Refresh and All-Module Clock Stop Mode

This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of

all on-chip peripheral modules by setting the ACSE bit in MSTPCRA to 1 (MSTPCRA,

MSTPCRB = H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to

F]FFFFFF), then execute the SLEEP instruction to enter the sleep mode.

In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the

clock for the bus controller is stopped, an auto-refresh cycle cannot be performed. When external

SDRAM is used and the contents of the SDRAM in sleep mode should be held, clear the ACSE bit

in MSTPCE to 0.

For details, see section 28.2.2, Module Stop Control Registers A and B (MSTPCRA and

MSTPCRB).

9.11.14

Setting SDRAM Mode Register

To use SDRAM, the mode register must be specified after a power-on reset.

Setting the MRSE bit in SDCR to 1 enables the SDRAM mode register setting. After this, write to

the SDRAM space in bytes.

When the value to be set in the SDRAM mode register is x, write to the following memory

location (address). The value of x is written to the SDRAM mode register.

• H'4000000/H'400000 + x for 8-bit bus SDRAM

• H'4000000/H'400000 + 2x for 16-bit bus SDRAM

The SDRAM mode register latches the address signals when the MRS command is issued.

This LSI does not support the burst read/burst write mode of SDRAM. When setting the SDRAM

mode register, use the burst read/single write mode and set the burst length to 1. Setting in the

SDRAM mode register must be consistent with that in the bus controller.

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