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R4S2426 bảng dữ liệu(PDF) 97 Page - Renesas Technology Corp |
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R4S2426 bảng dữ liệu(HTML) 97 Page - Renesas Technology Corp |
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97 / 1302 page ![]() Section 2 CPU Rev. 1.00 Sep. 19, 2008 Page 69 of 1270 REJ09B0466-0100 op op rn rm NOP, RTS, etc. ADD.B Rn, Rm, etc. MOV.B @(d:16, Rn), Rm, etc. rn rm op EA (disp) op cc EA (disp) BRA d:16, etc. (1) Operation field only (2) Operation field and register fields (3) Operation field, register fields, and effective address extension (4) Operation field, effective address extension, and condition field Figure 2.11 Instruction Formats (Examples) 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. |
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