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H8SX1663 bảng dữ liệu(PDF) 734 Page - Renesas Technology Corp |
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H8SX1663 bảng dữ liệu(HTML) 734 Page - Renesas Technology Corp |
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734 / 1158 page ![]() Section 15 Serial Communication Interface (SCI, IrDA, CRC) Rev.1.00 Jun. 07, 2006 Page 682 of 1102 REJ09B0294-0100 Table 15.4 shows sample N settings in BRR in normal asynchronous mode. Table 15.5 shows the maximum bit rate settable for each operating frequency. Tables 15.7 and 15.9 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be selected. For details, see section 15.7.4, Receive Data Sampling Timing and Reception Margin. Tables 15.6 and 15.8 show the maximum bit rates with external clock input. When the ABCS bit in the serial extended mode register_2, 5, and 6 (SEMR_2, 5, and 6) of SCI_2, 5, and 6 are set to 1 in asynchronous mode, the bit rate is two times that of shown in table 15.4. Table 15.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency P φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 4800 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 9600 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16 19200 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34 31250 0 7 0.00 0 9 –1.70 0 9 0.00 0 11 0.00 38400 0 7 0.00 0 7 1.73 0 9 –2.34 |
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