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HD6432351 bảng dữ liệu(PDF) 251 Page - Renesas Technology Corp |
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HD6432351 bảng dữ liệu(HTML) 251 Page - Renesas Technology Corp |
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251 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 217 of 988 REJ09B0330-0300 (2) Block Transfer Mode ETCRA: Holds block size Bit ETCRAH Initial value R/W : : : : *: Undefined 15 * R/W 14 * R/W 13 * R/W 12 * R/W 11 * R/W 8 * R/W 10 * R/W 9 * R/W 7 * R/W 6 * R/W 5 * R/W 4 * R/W 3 * R/W 0 * R/W 2 * R/W 1 * R/W Block size counter Bit ETCRAL Initial value R/W : : : : ETCRB: 0 * R/W 2 * R/W 1 * R/W 3 * R/W 4 * R/W 5 * R/W 6 * R/W 7 * R/W 8 * R/W 9 * R/W 10 * R/W 11 * R/W 12 * R/W 13 * R/W 14 * R/W 15 * R/W Bit ETCRB Initial value R/W : : : : Block Transfer Counter In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. |
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