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HD6432351 bảng dữ liệu(PDF) 240 Page - Renesas Technology Corp |
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HD6432351 bảng dữ liệu(HTML) 240 Page - Renesas Technology Corp |
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240 / 1025 page ![]() Section 7 DMA Controller (DMAC) Rev. 3.00 Sep 15, 2006 page 206 of 988 REJ09B0330-0300 Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE DMABCR DTIE Description 0 0 Transfer in sequential mode (no transfer end interrupt) (Initial value) 1 Transfer in sequential mode (with transfer end interrupt) 1 0 Transfer in repeat mode (no transfer end interrupt) 1 Transfer in idle mode (with transfer end interrupt) For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode. Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE Bit 4 DTDIR Description 0 0 Transfer with MAR as source address and IOAR as destination address (Initial value) 1 Transfer with IOAR as source address and MAR as destination address 1 0 Transfer with MAR as source address and DACK pin as write strobe 1 Transfer with DACK pin as read strobe and MAR as destination address |
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