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HD6432351 bảng dữ liệu(PDF) 181 Page - Renesas Technology Corp

tên linh kiện HD6432351
Giải thích chi tiết về linh kiện  16-Bit Single-Chip Microcomputer
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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HD6432351 bảng dữ liệu(HTML) 181 Page - Renesas Technology Corp

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Section 6 Bus Controller
Rev. 3.00 Sep 15, 2006 page 147 of 988
REJ09B0330-0300
6.3.6
Chip Select Signals
The H8S/2350 Group can output chip select signals (
CS0 to CS7) to areas 0 to 7, the signal being
driven low when the corresponding external space area is accessed. In normal mode, only the
CS0
signal can be output.
Figure 6.3 shows an example of
CSn (n = 0 to 7) output timing.
Enabling or disabling of the
CSn signal is performed by setting the data direction register (DDR)
for the port corresponding to the particular
CSn pin.
In ROM-disabled expansion mode, the
CS0 pin is placed in the output state after a power-on reset.
Pins
CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding
DDR should be set to 1 when outputting signals
CS1 to CS7.
In the H8S/2351’s ROM-enabled expansion mode, pins
CS0 to CS7 are all placed in the input
state after a power-on reset, and so the corresponding DDR bits should be set to 1 when outputting
signals
CS0 to CS7.
For details, see section 9, I/O Ports.
When areas 2 to 5 are designated as DRAM space, outputs
CS2 to CS5 are used as RAS signals.
Bus cycle
T1
T2
T3
Area n external address
Address bus
φ
CSn
Figure 6.3
CSn
CSn
CSn
CSn Signal Output Timing (n = 0 to 7)



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