HD6432351 datasheet(133/1025 Pages) RENESAS

133 / 1025 page

Section 5 Interrupt Controller

Rev. 3.00 Sep 15, 2006 page 99 of 988

REJ09B0330-0300

5.3

Interrupt Sources

Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (42

sources).

5.3.1

External Interrupts

There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can

be used to restore the H8S/2350 Group from software standby mode.

NMI Interrupt

NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of

the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt

is requested at a rising edge or a falling edge on the

NMI pin.

The vector number for NMI interrupt exception handling is 7.

IRQ7 to IRQ0 Interrupts

Interrupts IRQ7 to IRQ0 are requested by an input signal at pins

IRQ7 to IRQ0. Interrupts IRQ7 to

IRQ0 have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, at pins

IRQ7 to IRQ0.

• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.

• The interrupt priority level can be set with IPR.

• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0

by software.

A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.

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